Sponsored by IEEE Computer Society. In cooperation with NASA Goddard Space Flight Center and USRA/CESDIS
Frontiers '96 features two workshops in areas of rapidly
growing interest to the high-performance computing community. The
topics of the workshops are 1) The Petaflops Frontier, and 2)
Domain Specific Systems. These day and a half workshops are
organized to provide a forum for presenting the most recent
advances across a broad range of related topics within these
interdisciplinary fields. Mixed with the presentations are open
discussions on key topics from emerging technologies that may
impact future directions to the policies establishing those
directions. For more information contact the Program Chair at
frontiers96@cesdis.gsfc.nasa.gov.
Frontiers '96 is the sixth in a series of meetings on massively
parallel computation, focusing on research related to systems
scalable to many hundreds of processors. The conference will
include 34 original research papers surrounding the central theme
of research related to the exploitation of massive parallelism,
and any aspects of the design, analysis, development, and/or use
of massively parallel computers. The realm of computing considered
includes general purpose, domain specific, and special purpose
systems and techniques. Other highlights include two panels,
invited speakers, two pre-conference workshops, and conference
banquet. Of special note are two sessions discussing interim
results of eight Point Design Studies of high performance
computing environments - awardees of the proposals solicited by
the New Technologies Program in ASC (NSF), the Microelectronics
Systems Architecture Program in MIPS (NSF), the Computer Systems
Program in CCR (NSF), and in collaboration with DARPA and NASA.
10:30 - 12:00 Concurrent Sessions
Session 2A: Scheduling 1, Gyungho Lee, University of Texas
Session 2B: Routing, Walter B. Ligon, III, Clemson University
1:30 -3:30 pm Concurrent Sessions
Session 3A: Applications & Algorithms, Phyllis E. Crandall, University of Connecticut
Session 3B: Petaflops Computing / Point Design Studies, Paul H. Smith, Department of Energy
4:00 -5:30 pm Panel Session
Panel Session How Do We Break the Barrier to the Software Frontier?, Paul Messina, California Institute of Technology
10:30 am - 12 pm Concurrent Sessions
Session 5A: Scheduling 2, Danny Z. Chen, University of Notre Dame
Session 5B: SIMD, David Schimmel, Georgia Institute of Technology
1:30 -3:30 pm Concurrent Sessions
Session 6A: I/O Techniques, Steven Hotovy, Cornell Theory Center
Session 6B: Memory Management, Larry Meadows, The Portland Group
4:00 -5:30 pm Panel Session
Panel Session Petaflops Alternative Paths, Paul Messina, California Institute of Technology
10:30 am - 12 pm Concurrent Sessions
Session 8A: Synchronization, William Carlson, IDA Center for Computing Science
Session 8B: Networks, H. J. Siegel, Purdue University
1:30 pm -3:30 pm Concurrent Sessions
Session 9A: Performance Analysis, Tarek El-Ghazawi, George Washington University
Session 9B: Petaflops Computing / Point Design Studies, Wally Kleinfelder, Supercomputer Research Center
Sunday, October 27 1:00 - 5:00
Monday, October 28 8:30 - 5:00
Workshop A: The Petaflops Frontier - Parts 1 & 2
George Lake, University of Washington, Chair
The second workshop in this series explores the scaling properties of application algorithms, alternative architecture models, and device technology as they contribute to the feasibility of achieving computing performance in the regime of 10^15 operations per second. This is the only such workshop open to the general community and is an important forum for presenting new ideas.
13:00 Welcome, Objectives: GL and LS
13:15 Keynote, TERA Looks at Peta: Issues in Compilers and Operating Systems Burton Smith, Tera Computer Company
14:00 An Introduction to Petaflop Point Design Studies --John von Rosendale, The National Science Foundation
14:15 Architecture and Technology, Session A; Larry Snyder, Chair
15:30 BREAK
15:55 Architecture and Technology Session B; Larry Snyder, Chair
18:00 ADJOURN
08:00 Coffee
09:00 Architecture and Technology Session C; Larry Snyder, Chair
10:15 BREAK
10:45 Panel of Architecture and Technology Issues, Larry Snyder, Chair
Panel participants: All Speakers so far.
11:45 Lunch
13:00 Applications and System Software Session; Peter Kogge, Chair
15:30 Break
16:00 Panel and Floor Discussion on any and all Petaflop Issues, George Lake
17:45 Closing Comments, GL and LS
18:00 ADJOURN WORKSHOP
Jose Fortes, Purdue University, Chair
This new series of workshops is intended to highlight systems architecture and software that exploit the opportunity of alternative structures and methods to achieve very high performance for possibly narrow ranges of applications. Topics include special purpose or embedded processors, reconfigurable architectures, SIMD, digital signal processors, image processors, data compression devices, and other application-driven designs.
1.00 pm - 1.10 pm - Opening remarks, J. Fortes
1:10 pm - Session on Domain-specific hardware systems, J. Fortes, Chair
1:15 pm - 1:45 pm - Evaluating SIMD Arrays for Domain Specific Applications
Using ENPASSANT, M. Herbrordt and C. Weems, University of Houston and University of Massachusetts, USA.
1.45 pm - 2.15 pm - Efficient RMESH Algorithms for String Matching, H. C. Lee and F. Ercal, Dept. of Computer Science, University of Missouri-Rolla, USA.
2:15 pm - 2:45 pm - A 3.2 TOPS Enhanced Motion Estimation System, J. Berns and T. Noll, University of Technology RWTH Aachen, Germany.
2:45 pm - 3:00 pm BREAK
3:00 pm - 3:30 pm - Highly Parallel Computing for Solving Partial Differential Equations, I. Martin-Llorente and F. Tirado, Universidad Complutense, Spain.
3.30 pm - 4.00 pm - Parallel Programming by Data Queue Processing, P. Baglietto, M. Maresca, M. Migilardi, N. Zingirian, University of Genova and University of Padua, Italy.
4:00 pm - 4:30 pm - Session closing discussion and adjourn.
8:30 am - 10:30 am - Working session on Reconfigurable Architectures
Chair: Dennis Hawver, Annapolis Micro Systems
10:30 am - 10:45 am - Break
10:45 am - 12:30 pm - Working session on Reconfigurable Architectures
Moderator: Dennis Hawver, Annapolis Micro Systems
2:00 pm - Session on Domain-specific software and heterogeneous systems,
Jose Fortes, Chair
2:00 pm - 2:30 pm - Ct++: An Approach for a Retargetable High-Level Programming Environment for Image Processing Architecture, M. Pic, F. Bodin and H. Essafi, LETI and IRISA, France.
2:30 pm - 3:00 pm - An Application Domain Specific Language for Describing Board Games, J. Romein, H. Bal and D. Grune, Vrije Universiteit, The Netherlands.
3:00 pm - 3:30 pm - Products and Processes that Drive Domain-specific Architectures, L. Coglianese, LGA, Inc., USA
3:30 pm - 4:00 pm - Domain-specific Processing in the Context Heterogeneous Computing, H. J. Siegel, Purdue University, USA
4:00 pm - 5:00 pm - Floor discussion and Adjourn
8:45 - 9:00 am
Opening Remarks: Thomas Sterling, JPL/California Institute of Technology
9:00 - 10:00 am
Session 1: Invited Speaker - John
Hopson, Accelerated Strategic Computing Initiative (ASCI)
"From ASCI to Teraflops"
10:00 - 10:30 am Break
10:30 am - 12 noon Concurrent Sessions
Session 2A: Scheduling 1
Gang Scheduling for Highly Efficient Distributed Multiprocessor
Systems,
H. Franke, IBM T. J. Watson Research Center, P. Pattnaik, L.
Rudolph, Hebrew University
Integrating Polling, Interrupts, and Thread Management,
K. Langendoen, J. Romein, R. Bhoedjang, Vrije
Universiteit
A Practical Processor Design for Multithreading,
L. Amamiya, T. Kawano, H. Tomiyasu, S. Kusakabe, Kyushu
University
Session 2B: Routing
Deadlock-Free Path-Based Wormhole Multicasting in Meshes*,
E. Fleury, P. Fraigniaud, Ecole Normale Superieure de
Lyon
Efficient Multicast in Wormhole-Routed 2D Mesh/Torus
Multicomputers: A Network-Partitioning Approach.
S. Y. Wang, C. W. Ho, National Central University , Y. C.
Tseng, Chung-Hua Polytechnic University
Turn Grouping for Supporting Efficient Multicast in Wormhole Mesh
Networks,
K. P. Fan, C. T. King, National Tsing Hua University
12 noon - 1:30 pm Conference Luncheon - Ceremony to Transfer
MPP from Goddard Space Flight Center to Smithsonian
Institution
Jim Fischer, NASA Goddard Space Flight Center; Paul Ceruzzi,
Curator, Smithsonian Institute
1:30 pm -3:30 pm Concurrent Sessions
Session 3A: Applications & Algorithms
A3: A Simple and Asymptotically Accurate Model for Parallel
Computation,
V. Kumar, A. Grama, University of Minnesota, S. Ranka,
University of Florida, V. Singh, IBM T. J. Watson Research
Center
Fault Tolerant Matrix Operations Using Checksum and Reverse
Computation,
Y. Kim, J. Plank, J. Dongarra, University of Tennessee
A Statistically-Based Multi-Algorithmic Approach for
Load-Balancing Sparse Matrix Computations,
S. Nastea, O. Frieder, T. El-Ghazawi, George Washington
University
Session 3B: Petaflops Computing / Point Design Studies
Pursuing a Petaflop: Point Designs for 100 TF Computers Using PIM
Technologies,
P. M. Kogge, S. C. Bass, J. B. Brockman, D. Z. Chen, E. H. M.
Sha, University of Notre Dame
Hybrid Technology Multi-Threaded Architecture,
G. Gao, McGill University, K. Likharev, SUNY, Stony Brook, P.
Messina, California Institute of Technology, T. Sterling,
JPL/Caltech
Design Studies on Petaflops Special-Purpose Hardware for
Astrophysical Particle Simulations,
S. L.W. McMillan, Drexel University, P. Hut, Institute for
Advanced Study, Princeton, J. Makino, University of Tokyo, M. L.
Norman, University of Illinois at Urbana-Champaign, F. J. Summers,
Princeton University
The Illinois Aggressive Cache-Only Memory Architecture
Multiprocessor - (I-ACOMA)
J. Torrellas, D. Padua, University of Illinois at
Urbana-Champaign
3:30 pm - 4:00 pm Break
4:00 pm - 5:30 pm Session 3B Panel Session - "How Do We
Break the Barrier to the Software Frontier?"
Rick Stevens, Argonne National Laboratory, Panel Chair
5:30 pm - 7:00 pm Cocktail Party and Reception
Wednesday, October 30
9:00 - 10:00 am Session 4: Invited Speaker -
Feng-Hsiung Hsu, IBM Research, TJ Watson Laboratory
"Parallelism in the Deep Blue Chess Automoton"
10:00 - 10:30 am Break
10:30 am - 12 noon Concurrent Sessions
Session 5A: Scheduling 2
Largest-Job-First-Scan-All Scheduling Policy for 2D Mesh-Connected
Systems,
S. M. Yoo, University of Texas at Arlington
Scheduling for Large-Scale Parallel Video Servers,
M. Y. Wu, State University of New York at Buffalo
Effect of Variation in Compile Time Costs on Scheduling Tasks on
Distributed Memory Systems,
S. Darbha, Rutgers University, S. Pande, University of
Cincinnati
Session 5B: SIMD
Processor Autonomy and It's Effect on Parallel Program
Execution,
D. Hawver, G. Adams III, Purdue University
Particle-Mesh Techniques on the MasPar,
C. Mobarry, NASA Goddard Space Flight Center, K. Olson, George
Mason University
Solving Irregular Problems on SIMD Architectures,
M. Y. Wu, W. Shu, State University of New York at
Buffalo
12 noon - 1:30 pm Lunch (on your own)
1:30 pm -3:30 pm Concurrent Sessions
Session 6A: I/O Techniques
Intelligent, Adaptive File System Policy Selection,
T. Madhyastha, D. Reed, University of Illinois, Urbana
An Abstract-Device Interface for Implementing Portable
Parallel-I/O Interfaces,
R. Thakur, W. Gropp, E. Lusk, Argonne National
Laboratory
PMPIO - A Portable Implementation of MPI-IO,
S. Fineberg, NAS/NASA Ames Research Center, P. Wong, B.
Nitzberg, C. Kuszmaul, MRJ., Inc.
Disk Resident Arrays: An Array-Oriented I/O Library for
Out-Of-Core Computations,
J. Nieplocha, Pacific Northwest National Laboratory, I. Foster,
Argonne National Laboratory
Session 6B: Memory Management
Hardware-Controlled Prefeching in Directory-based Cache Coherent
Systems,
W. Hu, P. Xia, Institute of Computing Technology, Academia
Sinica
Preliminary Insights on Shared Memory PIC Code Performance on the
Convex Exemplar SPP1000,
P. MacNeice, Hughes STX, C. Mobarry, NASA Goddard Space Flight
Center, J. Crawford, USRA, Thomas Sterling, JPL/Caltech
Scalability of Dynamic Storage Allocation Algorithms,
A. Iyengar, IBM Thomas J. Watson Research Center
An Interprocedural Framework for Determining Efficient Data
Redistributions in Distributed Memory Machines,
S. Gupta, S. Krishnamurthy, Ohio University
3:30 pm - 4:00 pm Break
4:00 pm - 5:30 pm Panel Session - "Petaflops Alternative
Paths"
David Bailey, NASA Ames Research Center, Panel Chair
5:30 pm - 7:00 pm Conference Banquet:
Invited Speaker - John Toole, National Coordination Office for
HPCC
"Direction and Goals in Advanced Computing - A Perspective on
the National Agenda"
Thursday, October 31
9:00 - 10:00 am
Session 7: Invited Speaker - Steven Wallach, HP-Convex
"Independence Day"
10:00 - 10:30 am Break
10:30 am - 12 noon Concurrent Sessions
Session 8A: Synchronization
A Fair Fast Distributed Concurrent-Reader Exclusive-Writer,
T. Johnson, J. Yoon, University of Florida
Locks Improvement Technique for Release Consistency in Distributed
Shared Memory Systems,
S. Fu, N. F. Tzeng, University of Southwestern
Louisiana
A Quasi-Barrier Technique to Improve Performance of An Irregular
Application,
H. Shah, J. Fortes, Purdue University
Session 8B: Networks
Performance Analysis and Fault Tolerance of Randomized Routing on
Close Networks,
M. Bhatia, Bowie State University, A. Youssef, George
Washington University
Performing BMMC Permutations in Two Passes Through the Expanded
Delta Network and MasPar MP-2,
L. Wisniewski, Thinking Machines Corporation, T. Cormen, T.
Sundquist, Dartmouth College
Macro-Star Networks: Efficient Low-Degree Alternatives to Star
Graphs for Large-Scale Parallel Architectures,
C. H. Yeh, E. Varvarigos, University of California, Santa
Barbara
12 noon - 1:30 pm Lunch (on your own)
1:30 pm -3:30 pm Concurrent Sessions
Session 9A: Performance Analysis
Modeling and Identifying Bottlenecks in EOSDIS,
J. Demmel, M. Ivory, S. L. Smith, University of California,
Berkeley
Tools-Supported HPF and MPI Parallelization of the NAS Parallel
Benchmarks,
C. Clemencon, W. Sawyer, K. M. Decker, J. Fritscher, B. J. N.
Wylie, V. R. Deshpande, P. A. R. Lorenzo, R. Ruhl, Swiss Center
for Scientific Computing, A. Endo, N. Masuda, F. Zimmerman, NEC
European Supercomputer Systems
A Comparison of Workload Traces from Two Production Parallel
Machines,
K. Windisch, V. Lo, University of Oregon, D. Feitelson, Hebrew
University, B. Nitzberg, NASA Ames Research Center, R. Moore, San
Diego Supercomputer Center
Morphological Image Processing on Parallel Machines,
H. J. Siegel, M. D. Theys, R. Born, M. Allemang, Purdue
University
Session 9B: Petaflops Computing / Point Design Studies
MORPH: A Flexible Architecture for Executing Component Software at
100 TeraOPS,
A. A. Chien, R. K. Gupta, University of Illinois at
Urbana-Champaign
Architecture, Algorithms and Applications for Future Generation
Supercomputers,
V. Kumar, A. Sameh, University of Minnesota
Hierarchical Processors-and-Memory Architecture for High
Performance Computing,
J. A.B. Fortes, R. Eigenmann, Purdue University, V. Taylor,
Northwestern University
A Scalable-Feasible Parallel Computer Implementing Electronic and
Optical Interconnections for 156 TeraOPS Minimum Performance,
S. G. Ziavras, H. Grebel, New Jersey Institute of Technology,
A. T. Chronopoulos, Wayne State University
3:30 pm Adjourn