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Frontiers'96
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October 27 - 31, 1996 ---- Annapolis, Maryland


The Petaflops Frontier

The second workshop in this series explores the scaling properties of application algorithms, alternative architecture models, and device technology as they contribute to the feasibility of achieving computing performance in the regime of 10^15 operations per second. This is the only such workshop open to the general community and is an important forum for presenting new ideas. Proceedings will be published by CESDIS.

Domain Specific Systems

This new series of workshops is intended to highlight systems architecture and software that exploit the opportunity of alternative structures and methods to achieve very high performance for possibly narrow ranges of applications. Topics include special purpose or embedded processors, reconfigurable architectures, SIMD, digital signal processors, image processors, data compression devices, and other application-driven designs. Proceedings will be published by CESDIS.

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Design: Larry Picha, Boeing Information Services, Inc.
Authorizing Official: Thomas Sterling, General Chair, Caltech/JPL
Last Update: 20 AUGUST 96/l.picha