RECOMMENDATIONS

1.0 MAJOR RECOMMENDATIONS

PERFORM DETAILED APPLICATIONS STUDIES: :
Develop a set of petaflops scale applications and characterize them in detail to expose operational factors that determine performance. Evaluate and project the performance of the three archtypical architectures including COTS-based MIMD, PIM, and Hybrid-Technology Multi-threaded using the petaflops application test suite.

DEMONSTRATE 100 K CONCURRENT THREADS: :
Through analysis and simulation, demonstrate that applications of economic and societal value can expose more than 100 thousand-way concurrency by supplying computing demands to between 100 K and 1 M parallel threads. Show that a petaflops architecture can manage and exploit this level of parallelism.

DEVELOP TECHNIQUES FOR LATENCY MANAGEMENT AT PETAFLOPS SCALE COMPUTING: :
Pursue approaches in hardware, software, and algorithms for minimizing the impact of system latency on performance. Develop a new family of algorithmic techniques for latency tolerance. Derive system structures that minimize average latency for a broad range of applications. Devise hardware mechanisms for efficient hiding of latency. Incorporate latency management strategies and policies in resource management system software.

DESIGN AND EVALUATE AN ENHANCED PIM PETAFLOPS ARCHITECTURE: :
Extend the results of the PIM architecture point design study to incorporate cache-only-memory-architecture (COMA) and possible latency management mechanisms for general purpose processing and evaluate through simulation.

DESIGN AND EVALUATE A HYBRID TECHNOLOGY PETAFLOPS ARCHITECTURE: :
Extend the results of the HTMT architecture point design study to achieve a detailed system design and evaluate through simulation. This will provide the basis for a future prototyping initiative.

ADVANCE SUPERCONDUCTING RSFQ TECHNOLOGY: :
Accelerate research in superconducting technology with an emphasis on rapid single flux quantum logic (RSFQ) to determine its potential as a basis for petaflops architecture and to provide the technological means for implementing a petaflops computer. Critical areas include RSFQ cache memory, submicron fabrication of LSI density superconducting devices, and high-bandwidth low-power external interconnect.

EXPLORE ALGORITHMS FOR SPECIAL PURPOSE AND RECONFIGURABLE STRUCTURES: :
Study algorithms to identify opportunities for performance acceleration through special purpose structures. By clustering similar algorithms, examine the possibility of exploiting reconfigurable logic to enhance generality of specialized architecture hardware.

CONDUCT STUDY OF OPTICAL MEMORY TECHNOLOGY FOR PETAFLOPS APPLICATIONS: :
Conduct a detailed analysis of the potential of optical holographic memory for significant reduction of semiconductor main memory. Identify key technological advances required to enable this technology as a practical storage mechanism.

ESTABLISH PROGRAMMATIC FRAMEWORK FOR ADVANCING GOALS OF PETAFLOPS COMPUTING: :
Required are formal procedures for capturing results of intermediate studies, assessing implications and directions, and establishing new inter-agency collaborative initiatives.

2.0 IMMEDIATE ACTIONS

• Conduct a detailed point design study of COTS based MIMD petaflops architecture.
• Perform detailed applications studies of the three archtypical petaflops architecture classes and determine the potential for special purpose structures.
• Develop latency tolerant algorithm methods.
• Design and simulate a hybrid technology architecture incorporating superconducting logic, optical communications, a semiconductor memory hierarchy, and a 3-D holographic storage.
• Develop an approach for accelerating progress in superconducting memory, submicron fabrication, and interconnect technology.

3.0 DETAILED RECOMMENDATIONS

3.1 ARCHITECTURE

3.1.1 NEW POINT DESIGN STUDIES:

While the point design studies provided a basis for considering a number of architectures and concepts, even at this early stage opportunites for additional design points were revealed as both interesting and important to characterizing the petaflops design space. These included:
A. A distributed memory architecture employing processors and memory employing superconducting logic.
B. An SMP on a chip merging PIM structure with COMA memory management.
C. Novel architectures that include exotic revolutionary (non-incremental) architecture concepts and technologies.
D. Special Purpose Devices (SPD) derived for key kernel algorithms.


3.1.2 LATENCY MANAGEMENT:

Latency is one of the most challenging aspects of achieving efficient operation of petaflops scale computing system. Latency research is needed in hardware and software. Areas of consideration to be pursued include:
A. latency tolerant algorithms
B. hardware mechanisms for hiding/tolerating latency
C. language facilities for managing latency
D. tools for measuring and managing latency
E. performance studies of distributed SMPs
F. enhance message passing


3.1.3 OVERHEAD MECHANISMS:

Overhead mechanisms include a broad range of hardware support for functionality specific to the management of parallelism or for the class of problems specifically intended for petaflops scale computers. The overhead question needs to be worked on continuously. Actions to be taken include the following:
A. study how far the emerging distributed shared memory concept can be extended.
B. undertake to identify and specify low level mechanisms within the hardware that can enhance efficiency.
C. explore on-the-fly compression as a means of reducing memory requirements, both for density and bandwidth.
D. identify and elaborate on mechanisms that will support the execution of more than 100 K concurrent threads efficiently.
E. provide high efficiency support mechanisms for critical system software capabilities.
F. explore design space and implications for application specific reconfigurable hardware accelerators/co-processors.


3.2 TECHNOLOGY

Technology advances are a pacing item towards the achievement of petaflops computing. Semiconductor technology will play a major role but may be complemented by the capabilities of alternative technologies as well. It is possible that the time to petaflops may be significantly reduced by appropriate use of a diversity of technologies. To advance this possibility, the following actions are considered:

3.2.1 Semiconductor

A. develop approaches to increasing DRAM bandwidth.

B. establish a consistent cost ``rule book'' for semiconductor and other relevant technologies to support meaningful comparative studies. This includes the design study of standard major components and evolution with respect to time to produce a roadmap to petaflops including short and intermediate milestones along multiple likely technology/architecture paths.

C. update the SIA roadmap and extend to include additional performance characteristics not currently included.

3.2.2 Superconducting Devices

A. support the SIA-like roadmap for emerging superconducting technology.

B. enhance current research in rsfq to examine its application to superconducting memory.

C. establish a path to fabrication of submicron superconducting logic.

D. take necessary action to achieve greater than 100 GHz chip-wide clock rate for superconducting chips.

3.2.3 Optical

A. Conduct a detailed analysis of the potential of optical holographic memory for significant reduction of semiconductor main memory. Identify key technological advances required to enable this technology as a practical storage mechanism.

B. Determine operational characteristics of free-space and guided optical interconnects for petaflops scale computing structures.

C. conduct preliminary investigation of potential and approach to holographic optical storage for reducing DRAM memory component of total system.

3.3 SYSTEM SOFTWARE

Consolidate a list of software related questions driven by the pds to be considered by the pd teams in preparation for petasoft. identify and prioritize system software requirements and research objectives at petasoft.

System software experts to work with applications developers to devise a set of efficient system software tools and programming interface constructs to expose system control mechanisms and operation.

Determine aspects of system software requirements and operation that are principally related to petaflops scale computing and significantly distinguished from teraflops computing or below.

3.4 APPLICATIONS/ALGORITHMS

Research is needed in novel latency tolerant algorithms that explores a wider range of the latency/bandwidth/memory space and which requires tools for measuring and managing latency.

Identify algorithms and applications that would be amenable to solution by special purpose architectures and evaluate performance and cost effectiveness.

Extend the findings of the Bodega Bay meeting in quantitative evaluation of application requirements for petaflops systems architecture.

Extend and standardize the applications profiles from Bodega Bay to include parallelism profiles, degree of parallelism, granularity, precision, instruction set mix, inter-processor communication, affinity, etc. This may be achieved by conducting point-design-study like initiatives in petaflops application characterization.

Demonstrate applications that engage more that 100 K concurrent threads.

Conceptualize exotic applications that may be enabled by the availability of petaflops computers.

Analyze PDS architectures against a common set of applications.

Develop a set of simple codes, Peta Kernels, that can be used for hand analysis of architecture concepts.

Create abstract models of archtypical petaflops architectures as targets for algorithmic design.

Search for applications with low memory requirements for early use of petaflops computers with high processor to memory ratio.

3.5 GENERAL/PROGRAMMATIC

Federal agencies need to establish a coherent approach and business model for funding and supporting a domestic supercomputing industry towards petaflops capability.

Establish a program for conducting detailed moderate-term design, simulation, and evaluation studies of selected architecture approaches to near-petaflops architecture. This represents the post-PDS phase of petaflops system exploration.

Establish the process by which the results of the PDS will be evaluated and assimilated into the evolving petaflops effort. Provide support for The Petaflops Frontier - 2 workshop as a forum for presenting these findings.

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