Design Process for Complex Electronics
complex electronics begins where all systems and subsystems begin -
with defining the requirements, the CE Design Flow is uniques for these devices.
requirements, the most elegant design or implementation could utterly
fail to meet the original need. Designing and implementing complex
electronics occurs within the context of the larger system, as shown in
the stylized diagram below.
for the complex electronics are driven by the system they are a part of
, the environment where they will be used and their safety criticality. A simple home appliance
will place fewer demands (requirements) on a device than a
sophisticated satellite application will. At a minimum, the home
appliance usually doesn't’t need to worry about high energy cosmic
particles that can cause single event upsets. Because these devices are
hardware, the process of complex electronics design involves looking at
both the chip capabilities and constraints (e.g. how many gates does it
have, how much power does it need) and how the design works with and
against those constraints and capabilities.
section covers the following topics:
Design Life Cycle
basic design flow starts with the decomposition of system or sub-system
requirements to the particular complex electronic device. After that is
completed, the engineers (CE specialists or other electronic designers)
take the requirements and generate a design, often in a hardware
description language (design entry). The design has to be
“compiled” for the device (design synthesis). Synthesis is
more complicated than just running a compiler, however. During
synthesis, the design is mapped to the logic gates of the device.
Simulations are used to verify that the design is correct and can meet
the requirements and performance goals.
implementation of complex electronics involves mapping of the logic
(design) to the chip. The placement of the logic blocks within the
chip, and the routing between blocks, are some of the processes that
occur during implementation. This process is loosely comparable to the
linking step in software, where the compiled program is fixed up for
the software environment it will operate in. At the end of the
implementation phase, the final step is to “burn” or
program the device.
the simulation that occurs before the design is committed to hardware
can find most defects, the actual hardware device needs to be tested in
the circuit. Real signals are applied and the real output is tested.
You usually can’t get the degree of testing with in-circuit
verification that you can with simulation, because inputting
out-of-range signals might be difficult, access to the hardware pins
might not be possible, and in real projects, someone always wants to
use the hardware as soon as it’s completed. However, functional testing
in a variety of conditions is an important verification step. Errors in
the silicon chip are possible. Errors induced by the tools are more
likely. And sometimes the real world acts differently than expected and
can influence how the device works.
Requirements and Specifications
first step in the design process is to understand (and document) the
functions the complex electronics device must perform and the
constraints under which it operates. Designing complex electronics
should start with creating the specification, and not with jumping into
the design process. The act of documenting the requirements has some
useful effects that actually can save you time in the long run:
- The design team thinks
through the issues and reaches agreement. Some issues are well
understood at a high level, but raise additional questions when
working at the hardware level.
- Interfaces to other
areas (software, other hardware) are defined and available for
review by all affected parties.
- Non-engineers can
understand what the chip or device is supposed to do.
- If the trade-offs and
rationales are documented, as well as the requirements, future
design changes will require less impact assessment.
- The requirements can be
reviewed to assure that they provide measurable, testable
traceability into the design and implementation can be performed -
which is vital in mission or safety-critical applications.
first step in creating a design for complex electronics is to choose
how you will enter (capture) your design. Early chip designs were
primarily performed with schematic capture. Schematic capture (also
called schematic entry) creates the electronic diagram, or schematic,
of the electronic circuit. This is usually done interactively with the
help of a schematic capture tool also known as schematic editor.
schematic capture works fine for simple designs, complex electronics
almost always require the use of a hardware description language (HDL).
HDLs are any languages that are used for formal description of
electronic circuits. These languages can describe the operation,
design, and simulation tests of the circuit. HDLs can show several
aspects of the design, including the temporal behavior and spatial
structure. One major difference between HDLs and software languages is
the aspect of timing and concurrency.
nice aspect of HDLs is that they can be used as “executable
specification” to simulate the circuit. Simulation software can
be part of the tool suite provided by the vendor or a third-party
program. Simulators read the HDL “code” and model the
structure and flow of the circuit through time.
primary description languages are VHDL and Verilog. Older HDLs, such as
ABEL and CUPL, are still in use, especially for simple designs. Another
trend in hardware description languages is to add hardware-specific
elements to software programming languages. JHDL is implemented on top
of the Java language. SystemC adds hardware constructs as a C++ class
library. Still, VHDL and Verilog are by far the most common hardware
description languages in use.
of the method chosen to input the design (a hardware description
language or schematic capture), a software tool (or tool suite) is
required. All major complex electronics vendors offer design tools
optimized for their devices at a relatively low cost. Third-party tools
are common, and can provide additional capability. These tools are also
often quite expensive. However, because the boundaries between design
entry, simulation, synthesis, and place-and-route are well defined,
designers can mix-and-match tools from different vendors.
suite may include the following types of tools:
- HDL capture and design
include configuration management
- HDL simulator
- Logic Analyzer
- Logic Synthesis (this is
a critically important tool)
- Layout (physical
- Design management
electronic devices are designed at several levels, and with several
“views”, or ways of looking at the device. Each of the
various views of the device is refined at each of the levels of
representation. The Y diagram below shows how all these views and
levels are related.
design approaches for complex electronics focuses on the
behavioral/functional aspects of the devices, and uses sophisticated
tools to create the appropriate structural and physical aspects of the
design. Earlier design approaches required much more manipulation at
lower levels of the device circuit. With increasing complexity of the
devices, the design aspects have been moved “up” into a
more abstract domain, and the grunt work of converting the design into
a usable circuit is left to the tools. This abstraction allows the
designer and others to understand how the device functions within the
context of the system.
specification in a hardware description language consists of one or
more modules. The top level module specifies a closed system containing
both test data and hardware models. Component modules normally have
input and output ports. Events on the input ports cause changes on the
outputs. Events can be either changes in the values of wire variables
(i.e., combinational variables) or in the values of register variables, or can be explicitly generated abstract
events. Modules can represent pieces of hardware ranging from simple
gates to complete systems (e.g., microprocessors), and they can be
specified either behaviorally or structurally, or by a combination of
behavioral specification defines the behavior of a digital system
(module) using traditional programming language constructs (e. g., ifs,
assignment statements). This description of a complex electronic device
divides the device (chip) into several functional blocks that are
interconnected. A hardware description language (HDL) is used to
describe the behavior of each block. Functional blocks can be a finite
state machine, a set of registers and transfer functions, or even a set
of other interconnected functional blocks.
structural specification expresses the digital system (module) as a
hierarchical interconnection of sub modules. The components at the
bottom of the hierarchy are either primitives or are specified
behaviorally. It is in the structural specification that individual
inputs and outputs are defined. The structural specification may also
be called the architecture body.
synthesis is the process that takes the higher level designs and
optimally translates them to a gate-level design which can be mapped to
the logic blocks in a complex electronic device. It is during synthesis
that timing and area constraints can be specified by the user. Unlike
software which executes sequentially, the elements of a complex
electronic chip will execute in parallel, with specific timing
requirements. However, in general, you can think of synthesis as a form
of compiling, translating the readable language into instructions that
are implemented in the integrated circuit.
synthesis step transforms the behavioral and structural specifications
into an optimized netlist of gates. The netlist is just a description
of the various logic gates in the design and how they are
interconnected. During synthesis, the designer can optimize parameters
and constraints in the final chip. For example, a certain amount of
delay may be necessary when accessing an outside element like a sensor.
This delay can be included as a constraint during the synthesis
process. Other constraints may be power consumption and signal timing.
is used in the design of complex electronics at several levels. One
very nice aspect of hardware description languages is that they are
“executable”, and simulators that can run the code are very
common. Simulators are usually part of the tool suite provided by the
vendor of the complex electronic device (e.g., FPGA).
design entry, the design is simulated at the register-transfer level
(i.e., the HDL code). Simulation at this level is very fast, allowing
the designer to implement many simulations to fully understand how the
device will operate. Simulation can be used to help optimize the design
and refine the logic, though designers need to be careful not to use it
in the undisciplined software-style code-and-fix mode. Simulation of
the HDL code will look at signals and variables to check their value,
trace functions and procedures, and use breakpoints to check the status
of the device at specific events. This process is very similar to using
a software debugger. One caveat with simulation at this level of design
is that some properties are not yet defined, such as timing and
design synthesis, but before physical implementation, functional
simulation is used to help verify the design. The goal of functional
simulation is to ensure that the logic of the design does what you want
it to do, per the specification, and that it produces the correct
results. This type of simulation is very important to get as many bugs
out of the device as possible. If any errors are discovered, then the
design entry step is re-visited and necessary required changes are
made, leading to a successful simulation.
the design has been implemented, but before the device is actually
programmed, a final simulation with full timing information is
performed. The placement and routing process will determine any delays
and other timing information, which are back-annotated to the
gate-level netlist. This simulation is a much longer process, because
of the timing aspects. A static timing analysis might be substituted
for the timing simulation. Static timing analysis calculates the timing
of combinational paths between registers and compares it against the
designer’s timing constraints.
design has been created, simulated, and synthesized, the next step is
implementation of the design in the particular complex electronic
device. In software, implementation is usually translating the design
into source code and compiling it. In complex electronics design,
implementation is where the design meets the silicon - the higher level
design is converted into a chip layout.
implementation process uses the tools supplied by the device (e.g.,
FPGA) vendor. The functions that were defined in the design have to be
matched to the available blocks, gates, and other logic elements on the
chip. Some basic steps in implementing a design are:
- Place and Route
Floorplanning is the process
of identifying structures that should be placed close together, and
allocating space for them. In designing complex electronics, there are
multiple goals that must be met, and the goals often conflict. Finding
the best balance between the various goals and requirements is
something of an art. Some goals are:
- Minimize space on the
chip (allows choice of less costly chips)
- Meet or exceed required
- Place everything close
to everything else to minimize transmission time in the signal paths
does not have to be performed by the designer for many designs/chips.
Most tool suites will perform this step as part of the automated
sequence that takes the design and implements it in the chip. However,
if you are creating an ASIC, need the absolute best timing possible, or
are trying to cram a large design into a not-so-large chip, you will
probably need to actively floorplan.
converting the results of the synthesis process to the format supported
internally by the vendor’s place-and-route tools. The incoming
netlist is checked for adherence to design rules and is then optimized
for the chip.
Mapping takes the logic
blocks and determines what logic gates and interconnections on the
device should be used to implement those blocks. During the mapping
step, the functions within the device (such as counters, registers, or
adders) are aligned with the logic resources of the chip. The exact
process is device dependent. For example, FPGAs have look-up tables
that perform logic operations. The mapping tool (part of the
vendor’s tool suite) collects the gates defined by the netlist
into groups that will fit within the look-up tables.
and Route is the process of placing the logic blocks in the best
spots on the chip to achieve efficient routing. Items that the place
and route tool will look at include routing length (how far does a
signal have to travel), track congestion (how many signals are coming
into or out of an area), and path delays. While the process is usually
performed automatically by the vendor-supplied tools, the designer can
specify some parameters and constraints that the final layout has to
- the initial placement of
- a position for each
- a form factor
Programming the Device
design is successfully verified and found to meet timing and
performance requirements, the final step is to actually program the
device. At the completion of placement and routing, a binary
programming file is created. It’s used to configure the device.
The process of programming is usually dependent on the type of memory
used to store the device configuration and on the device type (e.g.,
FPGA or ASIC).
device is programmed, a set of functional tests are performed to verify
the device programming was correct, and that there are no silicon or
tool-induced defects that affect the device. The level of testing
performed depends on how critical the device is – mission or
safety critical devices will undergo more thorough functional tests
than those that play a less important role.
is a parallel set of activities to design and development. Various
tasks are performed at each phase of the development. The specific
verification activities, performed by either the electronic design
engineer or quality assurance, are listed in the appropriate life cycle phase.