Skip all navigation and jump to content

Jump to site navigation

NASA Logo

+ Visit NASA.gov

Assurance Process for Complex Electronics

Home

Complex Electronics Background

Complex Electronics Assurance Process

TECHNIQUES

CHECKLISTS

Site Map

Overview

Home

Getting Started

ROLES and RESPONSIBILITIES

Experience and Training

Process Assurance Overview

Links

Acronyms

Glossary

Print this section

Acronyms

A/D

Analog to Digital

ABEL

Advanced Boolean Equation Language

ADC

Analog to Digital Converter

ASIC

Application Specific Integrated Circuit

CE

Complex Electronics

CEAP

Complex Electronics Assurance Plan

CEH Complex Electronic Hardware

CIL

Critical Items List

CLB

Configurable/Complex Logic Block

CM

Configuration Management

CMM

Capability Maturity Model

COTS

Commercial Off-the-Shelf

CPLD

Complex Programmable Logic Device

CPU

Central Processing Unit

CRC

Cyclical Redundancy Checking

CUPL

Cornell University Programming Language

D/A

Digital to Analog

DSP

Digital Signal Processor

EDR

Engineering Design Review

EEPLD

Electrically Erasable Programmable Logic Device

EEPROM

Electrically Erasable Programmable Read-Only Memory

EPLD

Erasable Programmable Logic Device

EPROM

Erasable Programmable Read-Only Memory

ESD

Electrostatic Discharge

FAA

Federal Aviation Administration

FCA

Functional Configuration Audit

FIFO

First In First Out

FPGA

Field Programmable Gate Array

FMEA

Failure Modes and Effects Analysis

FTA

Fault Tree Analysis

GAL

Generic Array Logic

GPS

Global Positioning System

HDL

Hardware description language

I/O

Input/Output

IC

Integrated Circuit

IDMP

Input Data for Mask or Programming

IEEE

Institute of Electrical and Electronics Engineers

IP

Intellectual Property

ISS

International Space Station

JHDL

Java Hardware Description Language

JTAG

Joint Test Action Group

IT

Information Technology

MAPLD

Military-Aerospace Programmable Logic Devices (a yearly conference)

PAL

Programmable Array Logic

PCA

Physical Configuration Audit

PDA

Personal Digital Assistant

PL

Programmable Logic

PLA

Programmable Logic Array

PLC

Programmable Logic Controller

PLD

Programmable Logic Device

QA

Quality Assurance

RAM

Random Access Memory

ROM

Read Only Memory

SA

Software Assurance

SEI

Software Engineering Institute

SEU

Single Event Upset

SPLD

Simple Programmable Logic Device

SoaC

System-on-a-Chip

SoC

System-on-Chip

SRAM

Static Random Access Memory

SysML Systems Modeling Language

UML

Unified Modeling Language

V&V

Verification and Validation

VHDL

(Very High Speed Integrated Circuit) Hardware Description Language

VLSI

Very Large-Scale Integration

WYSIWYG

What You See Is What You Get

FirstGov logo

+ NASA Privacy, Security, Notices

NASA

Curator: Richard Plastow
NASA Official: Cynthia Calhoun
Last Updated: 10/14/2009