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Assurance Process for Complex Electronics


Complex Electronics Background

Complex Electronics Assurance Process



Site Map



Getting Started


Experience and Training

Process Assurance Overview




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Assurance Process for Complex Electronics

Purpose of this site

This web site provides details on an assurance process for complex electronics. This process is part of a research project that will help determine what assurance activities NASA organizations may be required to perform for complex electronics.

This web site also functions as an education tool for managers, systems engineers, and assurance engineers who are looking to learn more about complex electronics. The Getting Started link on the left will take you to a page that suggests what parts of the web site to look at, depending on your interest and experience.

What are complex electronics?

Complex electronics are Programmable Logic Devices (PLD) that can be used to implement specific hardware circuits. The devices that are included under the label of complex electronics are:

  • Complex Programmable Logic Device (CPLD)
  • Field Programmable Gate Array (FPGA)
  • Application Specific Integrated Circuit (ASIC)
  • System-on-Chip (SOC)
  • Field Programmable System Chip (FPSC)
  • Variations of FPGAs and ASICs

The CE Background section provides more information on these devices.

Site Overview

This web-site will help assurance engineers of all types create a comprehensive assurance plan for complex electronics. The assurance plan includes analyses, reviews, and techniques to use at each phase of the project life cycle. The individual tasks are provided under the Assurance Process tab.

The set of activities for a particular project will be a subset of the total list. Each project phase in the Assurance Process section will contain guidance on how to tailor the activities to projects with various levels of safety and mission risk.

While the assurance plan is the final result, the process of creating that plan requires trade-offs and tailoring. Therefore, this site also provides:

  • Information on the roles involved in creating and assuring complex electronics. This information can be used to assign responsibility for particular activities to individual team members.
  • Ideas for how to integrate the assurance plan with other project plans, and how to “sell” the project on the idea of complex electronics assurance.
  • An overview of complex electronics (CE Background).
  • Information on the design process for complex electronics, and a mapping from that process to the project life cycle.

Site Navigation

The horizontal navigation bar at the top has tabs for each major section in this web site. For each major section, there is a vertical navigation bar on the left side that links to sub-sections and pages within the major section.

The major sections (tabs) are:

  • Home. The home section contains general overview information, references, and general guidance. Getting Started suggests what parts of the web site to look at, depending on your interest and level of knowledge. Roles-Responsibilities describe the various roles, and associated responsibilities, for complex electronics. Training provides suggestions, with links, for types of training an assurance engineer should consider when working with complex electronics. Process Assurance briefly describes process and product assurance. The Links page has pointers to additional information that might be of interest. The Acronyms and Glossary links should be self-explanatory.
  • CE Background. The section main page provides an overview of the various types of complex electronics. Other pages describe the design process for the devices and map the complex electronics design activities to the project life cycle.
  • Assurance Process. This section is where you will find details on the assurance process. The section has sub-sections for each life cycle phase. Each phase sub-section has an overview, development, and assurance page.
  • Techniques. Most techniques included in the Assurance Process are referenced in their life cycle phase and also under the Techniques tab. If a technique is well documented within a NASA site, a link to the description is provided instead of a separate write-up. This section currently contains many techniques, but it does not contain all the possible techniques that can be used.
  • Checklists. Checklists can be used as an aid while performing the assurance process activities. The checklists need to be tailored to the project and the assurance classification of the complex electronics. Two types of checklists are included in this assurance plan:
    • Process checklists, used to verify a sequence of steps or activities was completed.
    • Review checklists, for various types of information (e.g. documents, code).
  • Site Map. The Site Map lists all the pages in this web site and provides a brief description of each page.

Each major section has a Print this Section link (left side navigation bar) that brings up a new window with a printer friendly page containing all the information in the section. The Assurance Process is an exception. Print this Section pages in the Assurance Process sub-sections contain all the information for a particular phase (e.g. planning or detailed design).

Motivation for a New Assurance Process

There are currently few specific, NASA-wide requirements or processes for assurance of complex electronics. Complex electronics are often overlooked when a comprehensive assurance strategy and plan are created for a project. Often, these devices are treated the same as any other electronic component, such as an off-the-shelf microprocessor or simple logic integrated circuit. However, such an approach does not address the design aspects, and associated errors, of complex electronics.

Programmable logic devices are now blurring the hardware/software boundary. FPGAs can have from 30,000 to over a million logic gates. System-on-Chip (SoC) devices combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. These devices can now be programmed to perform tasks that were previously handled in software, such as communication protocols. With increased complexity, the possibility of “software-like” bugs (incorrect design and logic) and unexpected interactions is greater. It is vital to be able to assure that the systems are designed and implemented correctly, tested fully, and reliable.

Besides problems with testing and verifying the designs and implementations of complex electronics, quality assurance is struggling with how to adequately deal with the “software-like” aspects of these devices. Some problems and concerns are:

  • ASICs and FPGAs have been used to avoid the rigors of the software assurance process. This results in fundamental verification matters being bypassed.
  • Complex Electronic devices are designed and programmed by electronic engineers (designers), often without quality assurance oversight or configuration management control of the designs. In addition, the development process may not be well defined or followed.
  • ASICs, FPGAs, and System-on-Chip (SoC) can contain embedded microprocessor cores with user-supplied software. They combine electronics and firmware into one chip. The presence of this firmware (i.e. software) is not always obvious to assurance personnel.
  • High-level languages (e.g. C, C++) are now being used to define complex electronic designs (in whole or in part).
  • Hardware quality assurance personnel may not be fully cognizant of the functions, potential problems, and issues with these devices.
  • Meaningful verification efforts require the person performing the verification to be knowledgeable about the complex electronic device and the tool suite used to create and implement the design.

Based on these perceived problems, NASA Headquarters is interested in defining assurance requirements for complex electronics. The assurance process developed by this research project will be validated by applying it to existing projects. The results will be provided to NASA Headquarters as one input into the decision process.


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Curator: Richard Plastow
NASA Official: Cynthia Calhoun
Last Updated: 12/14/2009