Implementation Phase

This Overview page for the Implementation Phase contains the following sections:

• Overview
• Implementation Process
• Entrance Criteria
• Exit Criteria
• Roles and Responsibilities
• Implementation Site Map

Overview

Once a design has been created, simulated, and synthesized, the next step is implementation of the design into the particular complex electronic device. The implementation process uses the tools supplied by the device (e.g., FPGA) vendor. The functions that were defined in the design have to be matched to the available blocks, gates, and other logic elements on the chip. Some basic steps in implementing a design are:

• Floorplan
• Translate
• Map
• Place and Route

Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them. In designing complex electronics, there are multiple goals that must be met, and the goals often conflict. Finding the best balance between the various goals and requirements is something of an art. Some goals are:

• Minimize space on the chip (allows choice of less costly chips)
• Meet or exceed required performance
• Place everything close to everything else to minimize transmission time in the signal paths

Translation involves converting the results of the synthesis process to the format supported internally by the vendor's place-and-route tools. The incoming netlist is checked for adherence to design rules and is then optimized for the chip.

Translation may also be referred to as compilation or compiling. This process is automatic, but it takes some wading through the reports produced by the tool to verify that the translation/compile was correct. An intelligent post-processor, rather than the designer (or worse, the quality assurance engineer), should be used to find syntax and binding errors - otherwise you will have to do this for each design modification!

Mapping takes the logic blocks and determines what logic gates and interconnections on the device should be used to implement those blocks. During the mapping step, the functions within the device (such as counters, registers, or adders) are aligned with the logic resources of the chip. The exact process is device dependent. For example, FPGAs have look-up tables that perform logic operations. The mapping tool (part of the vendor's tool suite) collects the gates defined by the netlist into groups that will fit within the look-up tables.

Place and Route is the process of placing the logic blocks in the best spots on the chip to achieve efficient routing. Items that the place and route tool will look at include routing length (how far does a signal have to travel), track congestion (how many signals are coming into or out of an area), and path delays. While the process is usually performed automatically by the vendor-supplied tools, the designer can specify some parameters and constraints that the final layout has to meet, including:

• the initial placement of the cells
• a position for each physical connector
• a form factor

Programming the device

Once the design is successfully verified and found to meet timing and performance requirements, the final step is to actually program the device. At the completion of placement and routing, a binary programming file is created. It's used to configure the device. The process of programming is usually dependent on the type of memory used to store the device configuration and on the device type (e.g., FPGA or ASIC). ASICs are manufactured, rather than programmed by the end-user, and verification of the design is critically important. Re-generating an ASIC is costly, both in dollars and in schedule time. FPGAs and other programmable devices are programmed by the end-user, either in-circuit or in a special programming device. Usually, a software tool running on a PC will interface with the programmable device and download the program using the appropriate format.

Implementation Process

The diagram below shows the implementation process for complex electronics. The Develop Implementation page describes the engineering process to create the design. The Assurance Process page describes the activities to assess and verify the design.

Entrance Criteria:

The following criteria should be met prior to beginning the implementation process.

• The design is reviewed and approved.
• Design synthesis was successful.
• Design verification and simulation was successfully performed.

Exit Criteria:

At the end of the implementation phase, the following criteria should be met:

• The device is programmed with the design.

Roles and Responsibilities

The table below describes typical activities during the Implementation Phase for both engineers and assurance personnel.

Implementation Site Map

The table below describes the information contained on the other pages in the Implementation section.