Implementation Process
Layout is a general term that includes floorplanning, mapping, translation, and place and route. The layout process generates the placement and routing information to meet the design rules, timing and other constraints. This phase provides reliable information about loads and coupling capacitors and the final design rule check that assures a verified netlist which can be forwarded to the foundry (if an ASIC) or programmed in the chip (if a programmable logic device).
This section covers:
Layout generation
The following tasks are performed as part of the layout process. As with all tasks within a complex project, the process and results of the various tasks should be documented in some manner.
- Finalise the floorplan of the chip (ASIC primarily)
- Perform Place & Route (P&R) taking into account all layout constraints
- Perform netlist optimizations for timing and design rules if necessary
- Generate the power distribution
- Generate the clock distribution (clock tree and buffers)
- Insert core and pad ring power distribution and possibly additional test pads in the circuit
- Determine the die size (ASIC only)
- Generate the bonding diagram respecting bonding and package constraints (ASIC only)
- Generate the Input Data for Mask or Programming file generation (IDMP).
Layout verification
Once layout is complete, it has to be verified to be correct before it is programmed in the device or sent to the manufacturer. The following tasks are typically performed:
- Layout Design Rule Check (DRC).
- Electrical Rule Check (ERC), check cross-talk sensitivity.
- Extract a netlist from the layout given in terms of IDMP.
- Verify that the post-layout netlist is consistent with the layout representing IDMP by performing a Layout Versus Schematic (LVS) comparison, or by performing a Netlist Comparison Check (NCC) between the post-layout netlist and the layout (IDMP) extracted netlist.
- Verify that the post-layout netlist is consistent in terms of functionality with the pre-layout netlist by simulation and/or formal methods.
- Extract the parasitic information. This delivers capacitance, resistance and inductivity values (only deep sub-micron technology), from which the actual delays are calculated for digital designs.
- Perform comprehensive post-layout verification. This is mostly accomplished by back-annotated simulations and timing analysis.
- Check relevant timing of l/Os.
- Perform transition check and load check on the nets inside the ASIC.
- ASIC/FPGA performances shall be characterized, such as max clock frequency, clock duty cycle, set-up and hold times for all inputs, propagation delays for all outputs.
Manufacturing and Programming
ASICs require many more steps than are provided here. Once the layout is complete and verified, the chip is sent to a manufacturer for production and testing. Additional tests are performed once the chips are returned, to verify functionality and correct operations.
FPGAs and other programmable devices require some form of "burning" to program the device. This is handled by a combination of software (on a desktop computer) and the programming device. The programming can, and should, be verified to be correct, possibly through a checksum or CRC value or by "reading out" the program and comparing it to the correct version.
At this point, the design has transitioned almost completely into the realm of hardware. The next phase is testing to verify the device implements all the requirements.
|
