Assurance Plan for Complex Electronics:

Overview and Background Information

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Assurance Process for Complex Electronics

Purpose of this site

This web site provides details on an assurance process for complex electronics. This process is part of a research project that will help determine what assurance activities NASA organizations may be required to perform for complex electronics.

This web site also functions as an education tool for managers, systems engineers, and assurance engineers who are looking to learn more about complex electronics. The Getting Started link on the left will take you to a page that suggests what parts of the web site to look at, depending on your interest and experience.

What are complex electronics?

Complex electronics are Programmable Logic Devices (PLD) that can be used to implement specific hardware circuits. The devices that are included under the label of complex electronics are:

  • Complex Programmable Logic Device (CPLD)
  • Field Programmable Gate Array (FPGA)
  • Application Specific Integrated Circuit (ASIC)
  • System-on-Chip (SOC)
  • Field Programmable System Chip (FPSC)
  • Variations of FPGAs and ASICs

The CE Background section provides more information on these devices.

Site Overview

This web-site will help assurance engineers of all types create a comprehensive assurance plan for complex electronics. The assurance plan includes analyses, reviews, and techniques to use at each phase of the project life cycle. The individual tasks are provided under the Assurance Process tab.

The set of activities for a particular project will be a subset of the total list. Each project phase in the Assurance Process section will contain guidance on how to tailor the activities to projects with various levels of safety and mission risk.

While the assurance plan is the final result, the process of creating that plan requires trade-offs and tailoring. Therefore, this site also provides:

  • Information on the roles involved in creating and assuring complex electronics. This information can be used to assign responsibility for particular activities to individual team members.
  • Ideas for how to integrate the assurance plan with other project plans, and how to “sell” the project on the idea of complex electronics assurance.
  • An overview of complex electronics.
  • Information on the design process for complex electronics, and a mapping from that process to the project life cycle.

Most techniques included in the assurance process are referenced in their life cycle phase and also under the Techniques tab. If a technique is well documented within a NASA site, a link to the description is provided instead of a separate write-up. Checklists are treated in the same way as the techniques. Types of checklists that are included in this assurance plan are:

  • Process checklists, used to verify a sequence of steps or activities was completed.
  • Review checklists, for various types of information (e.g. documents, code)

Motivation for a New Assurance Process

There are currently few specific, NASA-wide requirements or processes for assurance of complex electronics. Complex electronics are often overlooked when a comprehensive assurance strategy and plan are created for a project. Often, these devices are treated the same as any other electronic component, such as an off-the-shelf microprocessor or simple logic integrated circuit. However, such an approach does not address the design aspects, and associated errors, of complex electronics.

Programmable logic devices are now blurring the hardware/software boundary. FPGAs can have from 30,000 to over a million logic gates. System-on-Chip (SoC) devices combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. These devices can now be programmed to perform tasks that were previously handled in software, such as communication protocols. With increased complexity, the possibility of “software-like” bugs (incorrect design and logic) and unexpected interactions is greater. It is vital to be able to assure that the systems are designed and implemented correctly, tested fully, and reliable.

Besides problems with testing and verifying the designs and implementations of complex electronics, quality assurance is struggling with how to adequately deal with the “software-like” aspects of these devices. Some problems and concerns are:

  • ASICs and FPGAs have been used to avoid the rigors of the software assurance process. This results in fundamental verification matters being bypassed.
  • Complex Electronic devices are designed and programmed by electronic engineers (designers), often without quality assurance oversight or configuration management control of the designs. In addition, the development process may not be well defined or followed.
  • ASICs, FPGAs, and System-on-Chip (SoC) can contain embedded microprocessor cores with user-supplied software. They combine electronics and firmware into one chip. The presence of this firmware (i.e. software) is not always obvious to assurance personnel.
  • High-level languages (e.g. C, C++) are now being used to define complex electronic designs (in whole or in part).
  • Hardware quality assurance personnel may not be fully cognizant of the functions, potential problems, and issues with these devices.
  • Meaningful verification efforts require the person performing the verification to be knowledgeable about the complex electronic device and the tool suite used to create and implement the design.

Based on these perceived problems, NASA Headquarters is interested in defining assurance requirements for complex electronics. The assurance process developed by this research project will be validated by applying it to existing projects. The results will be provided to NASA Headquarters as one input into the decision process.

Getting Started

This web site provides a great deal of overview information and detail that is not necessary if you are simply creating a project-specific assurance plan for complex electronics. However, many assurance engineers are unfamiliar with complex electronics. The table below provides suggestions for the sections to look at, depending on your interests and experience.

Level of Information Desired

Sections to Look At

Develop the Complex Electronics Assurance Plan (CEAP) quickly

Go to Assurance Process→Planning→CE Assurance Plan. Use the provided template as a starting point.

Understand the assurance process in more detail, then develop the CEAP.

Go to the Assurance Process section. For each sub-section (Planning, V&V, etc.), read the overview and then the page listing the assurance activities. Peruse the Techniques section.

Understand the assurance and development processes in more detail, then develop the CEAP.

Read everything in the Assurance Process section. Read the Techniques section.

Focus on the development activities.

Go to the Assurance Process section. For each sub-section (Planning, V&V, etc.), read the overview and then the page listing the development activities.

High-level understanding

Read the Home and CE Background sections. Read the overview (main) pages of each Assurance Process section.

New assurance engineer learning about complex electronics.

Read Everything!

Roles and Responsibilities

A variety of people have responsibilities for the development and assurance of complex electronics (CE). These people are drawn from within the project, from assurance organizations, and possibly from other areas as well.

It is important to remember that the roles defined below may be filled by several individuals, or an individual may fulfill several roles. The roles, and associated responsibilities, should be divided among the appropriate personnel available to each project. The only caveat is that assurance requires a degree of independence. The person creating the complex electronics should not perform the assurance activities on it. However, in some cases, the assurance activities can be performed by another engineer or developer, when the available assurance engineers are lacking the necessary technical skills.

Role

Typical Organization

Responsibilities

Systems Engineer

Project Engineering

  • Define the system requirements
  • Decompose system requirements down to sub-system level
  • Maintain interfaces between sub-system and rest of system
  • Integrate the system
  • Define system-level testing

Electronics Designer

Project Engineering

  • Derive requirements for the board or chip level
  • Design electronics to meet the requirements, using good engineering practices
  • Define internal interfaces between parts of the electronics
  • Consider system aspects that may affect the electronics, including noise and power distribution.
  • Implement the design in hardware
  • Test the hardware; Implement corrections as necessary

CE specialist

(may be the Electronics Designer)

Project Engineering

  • Derive requirements for the complex electronics
  • Define internal interfaces
  • Design complex electronics to meet the requirements, using good design practices and tools
  • Ensure external interfaces match the specification, including voltage level and timing.
  • Implement the design
  • Simulate the design at various levels
  • Synthesize, place and route, etc. the design
  • Program the complex electronics
  • Test the final hardware; Implement corrections as necessary

System Safety

Assurance

  • Perform system safety analyses
  • Identify if complex electronics can cause a hazard or are part of a hazard control
  • Ensure that design errors in complex electronics are considered as a failure mode
  • Provide safety guidance to system designers
  • Verify safety features and controls are successfully implemented
  • Identify safety verifications required, including for complex electronics
  • Assess tools used to design and implement complex electronics for safety impacts

Quality Assurance

Assurance

  • Create QA plan; Include complex electronics assurance
  • Review subsystem requirements for proper decomposition from system requirements
  • Review design to verify requirements implemented, good engineering design practices followed
  • Assess implementation against the requirements and design
  • Ensure development and supporting processes (e.g. Configuration Management, ESD) are in place and followed
  • Review choice of parts; Provide guidance on preferred parts
  • Ensure electronics are assembled/manufactured to acceptable standards
  • Perform or witness testing at various system and subsystem levels
  • Ensure all requirements are adequately verified

CE Process Assurance

(new category)

Assurance, with possible help from Engineering

  • Assess entrance and exit criteria for each life cycle phase
  • Ensure traceability of the requirements through all levels of development
  • Analyze the products produced (documents, designs, etc.) against the requirements and the output of the previous phase
  • Assess the quality of the development process, and the level to which it is adhered
  • Perform white-box analyses on complex electronics designs and tests
  • Ensure all appropriate project plans are completed (to a sufficient level of detail) prior to when they should be used.

Configuration Management (CM)

 

  • Ensure software tools used for complex electronic design and programming are archived and controlled
  • Ensure complex electronic designs are captured in the CM system
  • Ensure changes to complex electronic designs are reviewed, evaluated for impacts, and approved
  • Provide official builds for formal programming/test
  • Ensure problem reporting, tracking, and corrective action occur for the system, including complex electronics

Reliability Engineer

Assurance or Project Team

  • Ensure that design-related failure modes and logic problems (for complex electronics) are considered in the analyses, including FMEA and FTA

Specific responsibilities and activities for each project life cycle phase, and for each of the various roles, are provided under the Assurance Process tab. Each individual phase has a chart listing all roles and associated processes.

Communication between all parties is vital to ensure that the complex electronics are designed and assured to the required level of quality. Electronic designers have to make sure that system safety and quality assurance are aware of the complex electronics, especially when it is used as part of a safety- or mission-critical subsystem. Quality assurance has to work with the electronic designers to tailor the assurance process to meet the risk and complexity of the project, system, or subsystem. Awareness of the presence of complex electronics is the first step to assuring the devices.

Assurance Engineer Experience and Training

Quality assurance engineers need to possess sufficient domain knowledge to evaluate the completeness and correctness of complex electronics requirements and design. They must have the ability to determine whether the design has incorporated all requirements accurately. If you are not an electrical engineer and do not have significant experience with complex electronics, you probably don't have that domain knowledge. For some process activities, you may wish to find an expert (either in the assurance arena or in engineering) to help you or to independently perform an analysis or evaluation. The most important aspect of assurance is evaluation by someone other than the designer, but not all evaluations have to be performed by the quality assurance engineer.

However, the majority of assurance activities for complex electronics can be performed by either hardware or software assurance engineers, with minimal training. Requirements verification and tracing, interface analysis, and many other tasks and analyses do not require in-depth domain knowledge. Process assurance activities (e.g., audits) are nearly the same across all assurance disciplines. What has to be learned is the terminology, the development process that will be followed, and a high-level understanding of the devices.

This assurance process web site provides some of the background information necessary for assurance engineers to perform assurance processes on complex electronics. Additional training will be helpful for those who are not familiar with complex electronics. In the table below, recommended topics are paired with training or information sources. The topics are recommendations only, and should not be construed as requirements on the assurance engineers. Likewise, the sources for training or information have been found to be useful, but are they are not the only means to acquire the knowledge.

Topic

Source of Information or Training

Basic Overview

Available from SATERN

  • Introduction to Complex Electronics
  • Complex Electronics Design Cycle
  • Assurance for Complex Electronics

Hardware Description Languages (HDL):

http://www.icd.com.au/vhdl.html (FPGA, VHDL)

http://equipe.nce.ufrj.br/gabriel/vhdlfpga.html (FPGA, VHDL)

Verilog

http://www.doulos.com/knowhow/verilog_designers_guide/

http://www.asic-world.com/verilog/veritut.html

VHDL

http://www.doulos.com/knowhow/vhdl_designers_guide/

http://www.gmvhdl.com/VHDL.html

http://instruct1.cit.cornell.edu/courses/ee475/tutorial/VHDLTut.htm

SystemC

http://www.doulos.com/knowhow/systemc/

http://www.systemc.org/

System Verilog

http://www.doulos.com/knowhow/sysverilog/

Devices (FPGAs, CPLDs, ASICs)

http://www.epanorama.net/links/fpga.html

http://www.mrc.uidaho.edu/fpga/index.php

http://www.fpga4fun.com/

http://www.fuse-network.com/fuse/training/index.html

http://www.edatoolscafe.com/books/ASIC/ASICs.php

http://www.cotsjournalonline.com/

http://www.fpgajournal.com/

Process Assurance

According to IEEE, quality assurance is defined as "a planned and systematic pattern of all actions necessary to provide adequate confidence that an item or product conforms to established technical requirements." Quality assurance (QA) can be broken down into two main areas: product assurance and process assurance.

Product assurance involves making sure that the final product meets its specifications. This is usually done via thorough testing. Ideally, it also includes verifying that the requirements are correct, the design meets the requirements, and the implementation reflects the design.

Process assurance looks at the process used to create that final product. Was the development effort planned? Were the plans followed, or just put on the shelf and ignored? Does the development process meet any required standards? Are best practices used to develop the product? In process assurance, QA provides management with objective feedback regarding compliance to approved plans, procedures, standards, and analyses.

Process assurance activities are performed throughout the life cycle, including product conception, design, implementation, operation, and maintenance. Process assurance will detect, record, evaluate, approve, track and resolve deviations from approved plans and procedures. For each life cycle phase, process assurance makes sure that planning is performed, that the plan is followed, and that the products of each phase are correct and complete. Note that verifying the quality of the requirements, design, and verifications are usually considered product assurance. This course includes them in process assurance because they are often overlooked when evaluating complex electronics.

For a circuit board that is assembled, product assurance would include verifying that the correct parts are on the board, assessing the quality of the soldering, and testing the board functionality. Process assurance activities would include verifying that the drawing used during the board assembly was configuration controlled and the correct revision, that proper Electrostatic Discharge (ESD) requirements were followed, and that an assembly process was defined and followed.

Links for Further Information

NASA-related Links

URL

Description

http://klabs.org/

NASA Digital Engineering Institute 

http://klabs.org/richcontent/Tutorial/tutorial.htm

Tutorials

http://ehw.jpl.nasa.gov/

JPL Evolvable Hardware laboratory

http://nepp.nasa.gov/index.cfm

NASA Electronic Parts and Packaging Program

Other Links

URL

Description

http://www.icd.com.au/vhdl.html

Links to tutorials, VHDL resources, and device information

http://www.epanorama.net/links/fpga.html

Links on FPGA design and verification, signal processing, and HDLs

http://www.cotsjournalonline.com/home/
article.php?id=100043

Article on FPGAs and reconfigurable computing

http://www.asic-world.com/verilog/veritut.html

Verilog HDL Tutorial

http://www.gmvhdl.com/VHDL.html

VHDL Tutorial

http://www.doulos.com/knowhow/

Portal to tutorials and other information on VHDL, Verilog, SystemC, and SystemVerilog

http://www.cs.ucr.edu/content/esd/labs/tutorial/

VHDL Tutorial

http://instruct1.cit.cornell.edu/courses/ee475/
tutorial/VHDLTut.htm

VHDL Tutorial with links to additional resources

http://www.systemc.org/

Information on SystemC

http://www.vhdl.org/

EDA (Electronic Design Automation) Industry Working Group web-site with many links to standards and information

http://www.vhdl.org/vhdlsynth/vhdlexamples/

VHDL Examples

http://www.mrc.uidaho.edu/fpga/index.php

Microelectronics Research and Communications Information (MRCI) search engine for FPGA information

http://www.fpga4fun.com/

FPGA projects, tutorials, and links to hardware boards

http://equipe.nce.ufrj.br/gabriel/vhdlfpga.html

Links to VHDL and FPGA resources

http://www.fuse-network.com/fuse/training/index.html

Training Material on programmable logic, circuit boards, microcontrollers, and ASICs

http://www.edatoolscafe.com/books/
ASIC/ASICs.php

ASIC on-line book

http://www.netrino.com/Articles/RCPrimer/

Reconfigurable Computing Tutorial

http://www.cotsjournalonline.com/home/

COTS Journal

http://www.fpgajournal.com/

FPGA Journal

 

Acronyms

A/D

Analog to Digital

ABEL

Advanced Boolean Equation Language

ADC

Analog to Digital Converter

ASIC

Application Specific Integrated Circuit

CE

Complex Electronics

CEAP

Complex Electronics Assurance Plan

CEH

Complex Electronic Hardware

CLB

Configurable/Complex Logic Block

CM

Configuration Management

CMM

Capability Maturity Model

COTS

Commercial Off-the-Shelf

CPLD

Complex Programmable Logic Device

CPU

Central Processing Unit

CRC

Cyclical Redundancy Checking

CUPL

Cornell University Programming Language

D/A

Digital to Analog

DSP

Digital Signal Processor

EDR

Engineering Design Review

EEPLD

Electrically Erasable Programmable Logic Device

EEPROM

Electrically Erasable Programmable Read-Only Memory

EPLD

Erasable Programmable Logic Device

EPROM

Erasable Programmable Read-Only Memory

ESD

Electrostatic Discharge

FAA

Federal Aviation Administration

FCA

Functional Configuration Audit

FIFO

First In First Out

FPGA

Field Programmable Gate Array

FMEA

Failure Modes and Effects Analysis

FTA

Fault Tree Analysis

GAL

Generic Array Logic

GPS

Global Positioning System

HDL

Hardware description language

I/O

Input/Output

IC

Integrated Circuit

IDMP

Input Data for Mask or Programming

IEEE

Institute of Electrical and Electronics Engineers

IP

Intellectual Property

ISS

International Space Station

JHDL

Just-Another Hardware Description Language

JTAG

Joint Test Action Group

IT

Information Technology

MAPLD

Military-Aerospace Programmable Logic Devices (a yearly conference)

PAL

Programmable Array Logic

PCA

Physical Configuration Audit

PDA

Personal Digital Assistant

PL

Programmable Logic

PLA

Programmable Logic Array

PLC

Programmable Logic Controller

PLD

Programmable Logic Device

QA

Quality Assurance

RAM

Random Access Memory

ROM

Read Only Memory

SA

Software Assurance

SEI

Software Engineering Institute

SEU

Single Event Upset

SPLD

Simple Programmable Logic Device

SoaC

System-on-a-Chip

SoC

System-on-Chip

SRAM

Static Random Access Memory

UML

Unified Modeling Language

V&V

Verification and Validation

VHDL

(Very High Speed Integrated Circuit) Hardware Description Language

VLSI Very Large-Scale Integration

WYSIWYG

What You See Is What You Get

 

Glossary

Antifuse

A two-terminal device that is normally a high resistive element and is programmed to a low impedance. 

Architecture

The common logic structure of a family of programmable integrated circuits. The same architecture may be realized in different manufacturing processes.

ASIC (Application Specific Integrated Circuit):

IC product customized for a single application.

Asynchronous

A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.

Boundary scan

Boundary scan is a methodology allowing complete controllability and observability of the boundary pins of a JTAG-compatible device via software control. This capability enables in-circuit testing without the need of in-circuit test equipment.

Cell Library

The collective name for the set of logic functions defined by the manufacturer of an Application-Specific Integrated Circuit (ASIC). The designer decides which types of cells should be realized and connected together to make the device perform its desired function.

Chip

Another name for an integrated circuit.

Codec

Short for compressor/decompressor, a codec is any technology for compressing and decompressing data. Codecs can be implemented in software, hardware, or a combination of both. Some popular codecs for computer video include MPEG, Indeo and Cinepak. 

Combinatorial

A digital function whose output value is directly related to the current combination of values on its inputs. Also known as combinational.

Comparator (digital)

A logic function that compares two binary values, and outputs the results in terms of binary signals representing less-than and/or equal-to and/or greater-than.

Configurable/Complex Logic Block (CLB)

The array of multi-input and multi-output logic cells to be programmed. CLB is a configurable logic block that consists mainly of Look-up Tables (LUTs) and flip flops. 

Cores

In the semiconductor design industry, refers to predefined functions such as processors or bus interfaces that are typically licensed from the software developer. Cores can be implemented directly in silicon, either in fixed logic or programmable logic devices, and saves chip designers time during product development. Synonymous with Intellectual Property.

CPLD (Complex Programmable Logic Device)

Programmable logic devices characterized by an architecture offering high speed, predictable timing and simple software.

Die

An unpackaged integrated circuit. In this case, the plural of die is also die.

Digital Signal

A digital signal is one whose key characteristic (e.g., voltage or current) fall into discrete ranges of values.  Most digital systems utilize two voltage levels (low and high values).

Digital Signal Processor (DSP)

A specialized CPU used for digital signal processing of signals such as sound, video, and other analog signals which have been converted to digital form. Some uses of DSP are to decode modulated signals from modems, to process sound, video, and images in various ways, and to understand data from sonar, radar, and seismological readings.

EEPROM (Electrically-Erasable Programmable Read-Only Memory)

A memory device whose contents can be electrically programmed by the designer. Additionally, the contents can be electrically erased allowing the device to be reprogrammed.

Electro-Static Discharge (ESD)

The term electro-static discharge refers to a charged person, or object, discharging static electricity. Although the current associated with such a static charge is low, the electric potential can be in the millions of volts and can severely damage electronic components.

EPROM (Erasable Programmable Read-Only Memory)

A memory device whose contents can be electrically programmed by the designer. Additionally, the contents can be erased by exposing the die to ultraviolet light through a quartz window mounted in the top of the component's package.

Falling-Edge

A transition from a logic 1 to a logic 0. Also known as a negative edge.

Firmware

Software programs, or sequences of instructions, that are hard-coded into non-volatile memory devices.

FIFO

First-in first-out

A data structure or hardware buffer where items come out in the same order they came in.

Flash memory

Non-volatile storage device similar to EEPROM, but where erasing can only be done in blocks or the entire chip.

Flip-flop

A digital logic circuit that can be switched back and forth between two states. 

FPGA (Field Programmable Gate Array)

High density PLD containing small logic cells interconnected through a distributed array of programmable switches. This type of architecture produces statistically varying results in performance and functional capacity, but offers high register counts. Programmability typically is via volatile SRAM or one-time-programmable antifuses.

Fuse

A two-terminal device that is normally a low resistive element and is programmed or "blown" resulting in an open or high impedance.

Gate

In electronic circuitry, a pathway that may be open or closed, depending on the source of the input, the strength of a signal, or the conductivity of chemicals used in semiconductors. Logic gates are programmed to correspond to related "if-then" statements. The state of an open or closed gate is analogous to the binary state of a 0 or a 1. The application of this analogy allows computing machinery with millions of gates to respond conditionally and to perform logical functions.

Gate Array

IC that is customized by interconnecting an array of logic elements. Customization is performed by the manufacturer and typically involves non-recurring engineering (NRE) costs and several design iterations.

Glue

Generic term for any interface logic or protocol that connects two component blocks. Hardware designers call anything used to connect large VLSIs or circuit blocks "glue logic."

Hardware Description Language (HDL)

A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. 

IC (Integrated Circuit)

A device in which components such as resistors, capacitors, diodes, and transistors are formed on the surface of a single piece of semiconductor.

In-Circuit Reconfigurable (ICR)

A SRAM-based or similar component which can be dynamically reprogrammed on-the-fly while remaining resident in the system.

In-System Programmable (ISP)

An EEPROM-based, FLASH-based, or similar component which can be reprogrammed while remaining resident on the circuit board.

JEDEC (Joint Electronic Device Engineering Council)

A council which creates, approves, arbitrates, and oversees industry standards for electronic devices. In programmable logic, the term JEDEC refers to a textual file containing information used to program a device. The file format is a JEDEC approved standard and is commonly referred to as a JEDEC file.

JHDL

JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit. More specifically, JHDL provides object classes used to build up circuit structure.

JTAG

Joint Test Action Group (JTAG, or "IEEE Standard 1149.1").

A standard specifying how to control and monitor the pins of compliant devices on a printed circuit board.

Logic

One of the three major classes of ICs in most digital electronic systems: microprocessors, memory, and logic. Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide.

Logic Function

A mathematical function that performs a digital operation on digital data and returns a digital value.

Logic Gate

The physical implementation of a logic function.

Logic Synthesis

A process in which a program is used to optimize the logic used to implement a design.

Look-Up Table (LUT)

An array or matrix of values that contains data that is searched. An alternative implementation of a CLB; the multiple inputs generate the complex outputs. 

Macrocell

A macrocell on most modern CPLDs contains a sum-of-products combinatorial logic function and an optional flip-flop. The combinatorial logic function typically supports four to sixteen product terms with wide fan in. Thus, a macrocell may have many inputs, but the logic function complexity is limited. On the other hand, most FPGA logic blocks have unlimited complexity, but the logic function only has four inputs.

Netlist

A list of names of symbols or parts and their connection points, which are logically connected in each net of a circuit. A file listing parameters extracted from a circuit schematic.

Noise

The miscellaneous rubbish that gets added to a signal on its journey through a circuit. Noise can be caused by capacitive or inductive coupling, or from externally generated interference.

Non-volatile

The memory elements keep their contents when power is removed from the device. 

Onboard

Contained on the device or on the board.

One Time Programmable

This device can be programmed only once; it's contents can not be changed.  While typically these devices are fuse or antifuse based, they can also be low-cost EPROM devices.  In this case, typically used for production devices, an inexpensive package is used without a window.

Partial Reprogrammability

The ability to leave the internal logic in place and change just one part of the FPGA.

Pinout

A diagram that indicates how wires are terminated to pins in a connector. A list that assigns device functions to specific pins.

Place and Route

Using backend implementation software tools, the process of connecting various memory elements in an FPGA to create a custom logic circuit.

Programmable Logic

A logic element whose function is not restricted to a particular function.  It may be programmed at different points of the life cycle.  At the earliest, it is programmed by the semiconductor vendor (standard cell, gate array), by the designer prior to assembly, or by the user, in circuit.

Programmable Logic Controller

A control device, usually used in industrial control applications, which employ the hardware architecture of a computer and relay ladder diagram language. Inputs to PLC’s can originate from many sources including sensors and the outputs of other logic devices. Also called "programmable controller".

Reconfigurable Computing

A methodology of using programmable logic devices in a system design such that the hardware-based logic can be changed to perform various tasks. Benefits include the use of fewer components, less power, and the flexibility that bring about. Also allows networked equipment in the field to be upgraded or repaired remotely.

Reprogrammable

These devices can have their configuration loaded more than once.  SRAM-based devices may be reloaded without restriction.  Many other forms of reprogrammable elements have restrictions on the number of write cycles, although they are high enough not to be of practical concern for most applications.  

Rising-Edge

A transition from a logic 0 to a logic 1. Also known as a positive edge.

RTL

Register Transfer Level

Register transfer level description, also called register transfer logic, is a description of a digital electronic circuit in terms of data flow between registers, which store information between clock cycles in a digital circuit. RTL description specifies what and where this information is stored and how it is passed through the circuit during its operation.

Sensor

A transducer that detects a physical quantity and converts it into a form suitable for processing. For example, a microphone is a sensor which detects sound and converts it into a corresponding voltage or current.

SRAM

Static Random Access Memory

A type of memory that is faster and more reliable than the more common DRAM (dynamic RAM). The term static is derived from the fact that it doesn't need to be refreshed like dynamic RAM, but it loses its memory if it's powered off.

Standard Cell

This device differs from the gate array since each cell may be different and optimized for each "standard" function.  There are no standard layers to the device and each layer of the chip is a unique design.

State Machine

The actual implementation (in hardware or software) of a function that can be considered to consist of a set of states through which it sequences.

Switch

A device for making or breaking an electric circuit, or for selecting between multiple circuits.

Synchronous

(1) A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. (2 )A system whose operation is synchronized by a clock signal.

Trace

A line or "wire" of conductive material – such as copper, silver, or gold – on the surface of or sandwiched inside a PCB, printed circuit board. These traces are often called individually a run. Traces carry an electronic signal or other forms of electron flow from one point to another.

Truth Table

A convenient way to represent the operation of a digital circuit as columns of input values and their corresponding output responses.

Verilog

A Hardware Description Language for electronic design and gate-level simulation. 

VHDL

Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

A Hardware Description Language for electronic design and gate-level simulation. 

Via

Feed-through. A plated through-hole in a printed circuit board used to route a trace vertically in the board, that is, from one layer to another. 

Volatile

The memory elements lose their contents when power is removed from the device.  SRAM-based devices are volatile and require another device to store their configuration program.