Failure Mode and Effect Analysis (FMEA)
A systematic process for identifying
potential design or process failures before they occur, with the intent
to eliminate or minimize the risk associated with them. Complex Electronics (CE) can use these same
techniques to determine potential problems. Signal Interfaces are a good
place to apply this technique. Remember,
since CE is a hardware/software mix, to include the software. Shown below is a simple example for a theoretical FPGA. The highest risk is listed in red and the next two highest are in yellow. Note that the error most likely to occur has a low risk priority.
| Mode of Failure |
Cause of Failure |
Effect of Failure |
Frequency (1-10) |
Severity (1-10) |
Chance of Detection (1-10) |
Risk Priority |
Design Action |
Design Validation |
| Data Loss |
Timing Error |
Major Loss of data |
2 |
9 |
8 |
144 |
|
Verify in timing runs |
| |
Bit Error |
Minor Loss of data |
4 |
1 |
10 |
40 |
Use CRC checks to validate data |
|
Verify in design review |
| Incorrect Data |
SEU |
Minor Loss of data |
2 |
2 |
7 |
28 |
Use latch back registers |
Verify in design review |
| |
Stuck Bit |
Minor Loss of data |
1 |
2 |
2 |
4 |
Use CRC checks to validate data |
Verify in design review |
| |
Timing Error |
Major Loss of data |
2 |
7 |
8 |
112 |
Increase hold times 10% |
|
| Chip Hang |
Wrong State entered |
Loss of all data |
1 |
10 |
10 |
100 |
Insure all unused states have an exit mode |
Verify in design review |
The
following links provide more information and examples of FMEA.
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